PDSP1601 MC

The PDSP1601 is a high performance 16-bit arithmetic

logic unit with an independent on-chip 16-bit barrel shifter.

The PDSP1601 supports Multicycle multiprecision

operation. This allows a single device to operate at 10MHz for
16-bit-bit-fields, 5MHz for 32-bit fields and 2.5MHz for 64-bit
fields. The PDSP1601 can also be cascaded to produce wider
words at the 10MHz rate using the Carry Out and Carry In pins.
The Barrel Shifter is capable of extension, for example the
PDSP1601 can used to select a 16-bit field from a 32-bit input
in 100ns.

Function

A7
A6
A5
A4
A3
A2
A1
A0

CEA

MSC

IS0
IS1
IS2
IS3

SV0
SV1
SV2
SV3

SVOE

RS0
RS1

Function

B7
B6
B5
B4
B3
B2
B1
B0

CEB

CLK

GND

MSA0
MSA1

A15
A14
A13
A12
A11
A10

A9
A8

GC pin

55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75

Function

VCC

RA0
RA1
RA2

IA0
IA1
IA2
IA3
IA4

MSB
MSS

B15
B14
B13
B12
B11
B10

B9
B8

GC pin

30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Function

VCC

RS2

C0
C1
C2
C3
C4
C5
C6
C7

GND

C8
C9

C10
C11
C12
C13
C14
C15

BFP

GC pin

5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

GC pin

80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

FEATURES

16-bit, 32 instruction 10MHz ALU

16-bit, 10MHz Logical, Arithmetic or Barrel Shifter

Independent ALU and Shifter Operation

4 x 16-bit On Chip Scratchpad Registers

Multiprecision Operation; e.g. 200ns 64-bit
Accumulate

Three Port Structure with Three Internal Feedback
Paths Elimates I/O Bottlenecks

300mW Maximum Power Dissipation

100-pin Ceramic Quad Flatpack

APPLICATIONS

Digital Signal Processing

Array Processing

Graphics

Database Addressing

High Speed Arithmetic Processors

Rev

C D

Date

MAR 1993 NOV 1998

NOTE

Polyimide is used as an inter-layer dielectric and glassivation.

Fig.1 Pin connections

PDSP1601 MC

ALU and Barrel Shifter

Supersedes April 1993 version, DS3763 - 1.1

DS3763 - 2.1 November 1998

GC100

ORDERING INFORMATION

PDSP1601/MC/GC1R

(Ceramic QFP Package -
MIL STD 883 Class B
Screening)

PDSP1601 MC

Symbol

MSB

MSS

B15 - B0

CEB

CLK

MSA0 - MSA1

A15 - A0

CEA

MSC

IS0 - IS3

SV0 - SV3

SVOE

RS0, RS1
RS2

C0 - C15

BFP

RA0 - RA2

IA0 - IA3
IA4

Vcc

GND

Description

ALU B-input multiplexer select control.

This input is latched internally on the rising edge

of CLK.

Shifter Input multiplexer select control.

This input is latched internally on the rising edge

of CLK.

B Port data Input. Data presented to this port is latched into the input register on the rising
edge of CLK. B15 is the MSB.

Clock enable, B Port input register. When low the clock to this register is enabled.

Common clock to all internal registered elements. All registers are loaded, and outputs
change on the rising edge of CLK.

ALU A-input multiplexer select control.

This input are latched internally on the rising edge

of CLK.

A Port data Input. Data presented to this port is latched into the input register on the rising
edge of CLK. B15 is the MSB.

Clock enable, A Port input register. When low the clock to this register is enabled.

C-Port multiplexer select control.1 This input is latched internally on the rising edge
of CLK.

Instruction inputs to Barrel Shifter, IS3 = MSB.

This input is latched internally on the

rising edge of CLK.

Shift Value I/O Port. This port is used as an input when shift values are supplied form
external sources, and as an output when Normalise operations are invoked. The I/O functions
are determined by the IS0 - IS3 instruction inputs, and by the

SVOE

control.

The shift value is latched internally on the rising edge of CLK.

SV Output enable. When high the SV port can only operate as an input. When low the SV
port can act as an input or as an output, according to the IS0 - IS3 instruction. This pin should
be tied high or low, depending upon the application.

Instruction inputs to Barrel Shifter registers.

These input are latched internally on the

rising edge of CLK.

C Port data output. Data output on this port is selected by the C output multiplexer.
C15 is the MSB

Output enable. The C Port outputs are in high impedance condition when this control is high

Block Floating Point Flag from ALU, active high.

Carry out from MSB of ALU

Instruction inputs to ALU registsers.

These inputs are latched interally on the rising

edge of CLK.

Carry in to LSB of ALU

Instruction inputs to ALU.

IA4 = MSB. These inputs are latched internally on the rising

edge of CLK.

+5V supply: Both Vcc pins must be connected.

0V supply: Both GND pins must be connected.

PIN DESCRIPTIONS

18 - 25
30 - 37

41 - 42

43 - 50
55 - 62

65 - 68

69 - 72

74 - 75
81

82 - 98

100

7 - 9

11 - 14

80, 5

90 & 40

Pin No.

(GG100

Package)

NOTES

1. All instructions are executed in the cycle commencing with the rising edge of the CLK which latches the inputs.

PDSP1601 MC

FUNCTIONAL DESCRIPTION

The PDSP1601 contains four main blocks: the ALU, the

Barrel Shifter and the two Register Files.

The ALU

The ALU supports 32 instructions as detailed in Table 1.
The inputs to the ALU are selected by the A and B MUXs.

Data will fall through from the selected register through the A
or B input MUXs and the ALU to the ALU output register file in
100ns.

The ALU instructions are latched, such that the instruction

will not start executing until the rising edge of CLK latches the
instruction into the device.

The ALU accepts a carry in from the CI input and supplies

a carry out to the CO output. Additionally, at the end of each
cycle, the carry out from the ALU is loaded into an internal 1
bit register, so that it is available as an input to the ALU on the
next cycle. In the manner, Multicycle, multiprecisiion
operations are supported. (See MULTICYCLE CASCADE
OPERATIONS).

BFP Flag

The ALU has a user programmable BFP flag. This flag

may be programmed to become active at any one of four
conditions. Two of these conditions are intended to support
Block Floating Point operations, in that they provide flags
indicating that the ALU result is within a factor of two or four of
overflowing the 16 bit number range. For multiprecision
operations the flag is only valid whilst the most significant 16
bit byte is being processed. In this manner the BFP flag may
be used over any extended word width.

The remaining two conditions detect either an overflow

condition or a zero result. For the overflow condition to be

active the ALU result must have overflowed into the 16th (sign)
bit, (this flag is only valid whilst the most significant 16 bit byte
is being processed). The zero condition is active if the result
from the ALU is equal to zero. For multiprecision operations
the zero flag must be active for all of the 16 bit bytes of an
extended word.

The BFP flag is programmed by executing on of the four

SBFXX instructions (see Table 1). During the execution of any
of these four instructions, the output of the ALU is forced to
zero.

Multicycle/Cascade Operation

The ALU arithmetic instructions contain two or three

options for each arithemtic operation.

The ALU is designed to operate with two's complement

arithmetic, requiring a one to be added to the LSB for all
subtract operations. The instructions set includes instructions
that will force a one into the LSB, e.g. MIAX1, AMBX1, BMAX1
(see Table 1).

These instructions are used for the least significant 16 bits

of any subtract operation.

The user has an option of cascading multiple devices, or

multicycling a single device to extend the arithmetic precision.
Should the user cascade multiple devices, then the cascaded
arithmetic instructions using the external CI input should be
employed for all but the least significant 16 bits, e.g. MIACI,
APBCI, BMACI (see Table 1).

Should the user multicycle a single device, then the

Multicycle Arithmetic instructions, using the internally
registered CO bit should be employed for all but the least
significant 16 bits, e.g. MIACO, APBCO, AMBCO, BMACO
(see Table 1).

A INPUT

A REG

A MUX

BFP

B MUX

MSA0-1

MSB

IA0-4

ALU

RAD-2

ALU REG FILE

LEFT REG.

RIGHT REG.

C MUX

MSC

COUT

SHIFTER REG FILE

LEFT REG.

RIGHT REG.

RS0-2

BARREL SHIFTER

SHIFT

CONTROL

SVOE

IS0-3

SV0-3

S MUX

MSS

B REG

CEB

B INPUT

CEA

Fig.2 PDSP1601 block diagram

PDSP1601 MC

Inst

00
01
02
03
04
05
06
07
08
09

0A
0B

0C
0D

0E
0F

IA4-IA0

00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111

Mnemonic

CLRXX

MIAX1

MIACI

MIACO

A2SGN

A2RAL

A2RAR
A2RSX

APBCI

APBCO

AMBX1

AMBCI

AMBCO

BMAX1

BMACI

BMACO

Operation

RESET
MINUS A
MINUS A
MINUS A
A/2
A/2
A/2
A/2
A PLUS B
A PLUS B
A MINUS B
A MINUS B
A MINUS B
B MINUS A
B MINUS A
B MINUS A

Mode

---------

LSBYTE

CASCADE

MULTICYCLE

MSBYTE

MULTICYCLE
MULTICYCLE
MULTICYCLE

CASCADE

MULTICYCLE

LSBYTE

CASCADE

MULTICYCLE

LSBYTE

CASCADE

MULTICYCLE

Function

CLEAR ALL REGISTERS
NA Plus 1
NA Plus CI
NA Plus CO
A/2 Sign Extend
A/2 with Ral LSB
A/2 with RAR LSB
A/2 with RSX LSB
A Plus B Plus CI
A Plus B Plus CO
A Plus NB Plus 1
A Plus NB Plus CI
A Plus NB Plus CO
NA Plus B Plus 1
NA Plus B Plus CI
NA Plus B Plus CO

Table 1 ALU instructions

1a. ARITHMETIC INSTRUCTIONS

Inst

10
11
12
13
14
15
16
17

IA4-AI0

10000
10001
10010
10011
10100
10101
10110
10111

Mnemonic

ANXAB
ANANB
ANNAB

ORXAB
ORNAB
XORAB

PASXA

PASNA

Operation

A AND B
A AND NB
NA AND B
A OR B
NA OR B
A XOR B
PASS A
INVERT A

Function

A. B
A. NB
NA. B
A + B
NA + B
A XOR B
A
NA

1c. CONTROL INSTRUCTIONS

Inst

18
19

1A
1B
1C
1D
1E
1F

IA4-AI0

11000
11001
11010
11011
11100
11101
11110
11111

Mnemonic

SBFOV

SBFU1
SBFU2
SBFZE

OPONE

OPBYT

OPNIB

OPALT

Operation

Set BFP Flag to OVR, Force ALU output to zero
Set BFP Flag to UND 1 Force ALU output to zero
Set BFP Flag to UND 2 Force ALU output to zero
Set BFP Flag to ZERO Force ALU output to zero
Output 0001 Hex
Output 00FF Hex
Output 000F Hex
Output 5555 Hex

KEY
A

= A input to ALU

= B input to ALU

= External Carry in to ALU

= Internally Registered Carry out from ALU

RAL

= ALU Register (Left)

RAR

= ALU Register (Right)

RSX

= Shifter Register (Left or Right)

MNEMONICS

CLRXX

Clear All Registers to zero

MIAXX

Minus A,

= Carry in to LSB

A2XXX

A Divided by 2,

XXX = Source of MSB

APBXX

A Plus B,

= Carry in to LSB

AMBXX

A Minus B,

= Carry in to LSB

BMAXX

B Minus A,

= Carry in to LSB

ANX-Y

AND

= Operand 1, Y = Operand 2

ORX-Y

= Operand 1, Y = Operand 2

XORXY

Exclusive OR

= Operand 1, Y = Operand 2

PASXX

Pass

= Operand

SBFXX

Set BFP Flag

= Function

OPXXX

Output Constant XXX

1b. LOGICAL INSTRUCTIONS

PDSP1601 MC

Divide by Two

The ALU has four (A2SGN, A2RAL, A2RAR, A2RSX)

instructions used for right shifting (dividing by two) extended
precision words. These words, (up to 64 bits) may be stored
in the two on-chip register files. When the least significant 16
bit word is shifted, the vacant MSB must be filled with the LSB
from the next most significant 16 bit byte. This is achieved via
the A2RAL, A2RAR or A2RSX instructions which indicate the
source of the new MSB (see SLU INSTRUCTION SET).

When the most significant 16 bit byte is right shifted, the

MSB must be filled with a duplicate of the original MSB so as
to maintain the correct sign (Sign Extension). This operation
is achieved via the A2SGN instruction (see Table 1).

Constants

The ALU has four instructions (OPONE, OPBYT, OPNIB,

OPALT) that force a constant value onto the ALU output.
These values are primarily intended to be used as masks, or
the seeds for mask generation, for example, the OPONE
instruction will set a single bit in the least significant position.
This bit may be rotated any where in the 16 bit field by the
Barrel Shifter, allowing the AND function of the ALU to perform
bit-pick operations on input data.

CLR

The ALU instruction CLRXX is used as a Master Reset for

the entire device. This instruction has the effect of:

1. Clearing ALU and Barrel Shifter register files to zero.
2. Clearing A and B port input registers to zero.
3. Clearing the R1 and R2 shift control registers to zero.
4. Clearing the internally registered CO bit to zero.
5. Programming the BFP flag to detect

overflow conditions.

The Barrel Shifter

The Barrel Shifter supports 16 instructions as detailed in

Table 2. The input to the Barrel Shifter is selected by the S
MUX. Data will fall through from the selected register, through
the S MUX and the Barrel Shifter to the shifter output register
file in 100ns.

The Barrel Shifter instructions are latched, such that the

instructions will not start executing until the rising edge of CLK
latches the instruction into the device.

The Barrel Shifter is capable of Logical Arithmetic or Barrel

Shifts in either direction.

Logical shifts discard bits that exit the 16 bit field and fill
spaces with zeros.

Arithmetic shifts discard bits that exit the 16 bit field and
fill spaces with duplicates of the original MSB.

Barrel Shifts rotate the 16 bit fields such that bits tha exit
the 16 bit field to the left or right reappear in the vacant
spaces on the right or left.

The amount of shift applied is encoded onto the 4 bit Barrel

Shifter input as illustrated in Table 3. The type of shift and the
amount are determined by the shift control block. The shift
control block (see Fig.3) accepts and decodes the four bit ISO-
3 instruction. The shift control block contains a priority
encoder and two, user programmable 4 bit registers R1 and
R2.

There are four possible sources of shift value that can be

passed onto the Barrel Shifter, there are:

1. The Priority Encoder
2. The SV input
3. The R1 register
4. The R2 register

Mnemonic

LSRSV

LSLSV

BSRSV

BSLSV
LSRR1
LSRR2

LSLR1
LSLR2

LR1SV
LR2SV

ASRSV
ASRR1
ASRR1

NRMXX
NRMR1
NRMR2

IS3-IS0

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Operation

Logical Shift Right by SV
Logical Shift Left by SV
Barrel Shift Right by SV
Barrel Shift Left by SV
Logical Shift Right by R1
Logical Shift Left by R1
Logical Shift Right by R2
Logical Shift Left by R2
Load Register 1 From SV
Load Register 2 From SV
Arithmetic Shift Right by SV
Arithmetic Shift Right by R1
Arithmetic Shift Right by R2
Normalise Output PE
Normalise Output PE, Load R1
Normalise Output PE, Load R2

Inst

0
1
2
3
4
5
6
7
8
9

A
B
C
D
E
F

I/O

I
I
I
I
X
X
X
X
I
I
I
X
X
O
O
O

Table 2 Barrel shifter instructions

KEY
SV

= Shift Value

= Register 1

= Register 2

= Priority Encoder Output

=> SV Port operates as an Input

=> SV Port operates as an Output

=> SV Port in a High Impedance State

MNEMONICS

LSXYY

Logical Shift,

= Direction YY = Source of Shift Value

BSXYY

Barrel Shift,

= Direction YY = Source of Shift Value

ASXYY

Arithmetic Shift, X

= Direction YY = Source of Shift Value

LXXYY

Load

= Target YY = Source

NRMYY Normalise by PE, Output PE value on SV Port, Load YY Reg

PDSP1601 MC

SV3

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

SV2

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

SV1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

SV0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Shift

No shift

1 place

2 places
3 places
4 places
5 places
6 places
7 places
8 places
9 places

10 places
11 places
12 places
13 places
14 places
15 places

(1)

Priority encode the 16 bit input to the Barrel Shifter and

place the 4 bit value in either of the R1 or R2 registers and

output the value on the SV port (if enabled by

SVOE

(2)

Shift the 16 bit input by the amount indicated by the

Priority Encoder such that the output from the Barrel Shifter is
a normalised value.

SV Input

If the SV port is selected as the source of the shift value,

then the input to the Barrel Shifter is shifted by the value stored
in the internal SV register.

SVOE

The SV port acts as an input or an output depending upon

the IS0-3 instruction. If the user does not wish to use the
normalise instructions, then the SV port mat be forced to be

input only by typing

SVOE

control high. In this mode the SV

port may be considered an extension of the instruction inputs.

R1 and R2 Registers

The R1 and R2 registers may be loaded from the Priority

Encoder (NRMR1 and NRMR2) or from the SV input (LR1SV,
LR2SV).

Whilst the latter two instructions are executing, the Barrel

Shifter will pass its input to the output unshifted.

Priority Encoder

If the priority encoder is selected as the source of the shift

value (instructions:- NRMXX, NRMR1, MRMRZ), then within
one 200ns cycle or two 100ns cycles, the shift circuitry will:

Table 3 Barrel shifter codes

MUX

PRIORITY ENCODER

INSTRUCTION

DECODE

IS0-3

SVOE

Fig.3 Shift control block

PDSP1601 MC

The Register Files

There are two on-chip register files (ALU and Shifter), each

containing two 16 bit registers and each supporting 8
instructions (see Table 4). The instructions fo the ALU register
file and the Barrel Shifter Register file are the same.

The Inputs to the register files come from either the ALU or

the Barrel Shifter, and are loaded into the Register files on the
rising edge of CLK.

The register file instructions are latched such that the

instruction will not start executing until the rising edge of the

CLK latches the instruction into the device.

The register file instructions (see Table 4) allow input data

to be loaded into either, neither or both of the registers. Data
is loaded at the end of the cycle in which the instruction is
executing.

The register file instructions allow the output to be sourced

from either of the two registers, the selected output will be valid
during the cycle in which the instruction is executing.

Operation

Load Left Reg Output Right Reg
Load Right Reg Output Left Reg
Load Left Register, Output Left Reg
Load Right Register, Output Right Reg
Load Both Register, Output Left Reg
No load Operation, Output Right Reg
No load Operation, Output Left Reg
No load Operation, Pass Barrel Shifter Result

Operation

Inst

0
1
2
3
4
5
6
7

RA2-RA0

000
001
010
011
100
101
110
111

Mnemonic

LLRRR
LRRLR

LLRLR

LRRRR

LBRLR

NOPRR

NOPLR
NOPPS

ALU REGISTER INSTRUCTIONS

Inst

0
1
2
3
4
5
6
7

RA2-RA0

000
001
010
011
100
101
110
111

Mnemonic

LLRRR
LRRLR

LLRLR

LRRRR

LBRLR

NOPRR

NOPLR
NOPPS

SHIFTER REGISTER INSTRUCTIONS

Table 4 ALU and shift register instructions mnemonics

MNEMONICS

LXXYY

Load XX = Target,

= Source of Output

LBOXX

Load Both Registers, XX

= Source of Output

NOPXX No Load Operation,

= Source of Output

PDSP1601 MC

INSTRUCTION SET

ALU Arithmetic Instructions

Function

On the rising edge of CLK at the end of the cycle in which this instruction is executing, the
A Port, B Port, ALU, Barrel Shifter, and Shift Control Registers will be loaded with zeros.
The internal registered CO will also be set to zero, and the BFP flag will be set to activate
on overflow conditions.

The A input to the ALU is inverted and a one is added to the LSB.

The A input to the ALU is inverted and the CI input is added to the LSB.

The A input to the ALU is inverted and the CO output from the ALU on the previous cycle
is added to the LSB.

The A input to the ALU is right shifted one bit position. The LSB is discarded, and the vacant
MSB is filled by duplicating the original MSB (Sign Extension).

The A input to the ALU is right shifted one bit position. The LSB is discarded, and the vacant
MSB is filled with the LSB from the ALU left register.

The A input to the ALU is right shifted one bit position. The LSB is discarded, and the vacant
MSB is filled with the LSB from the ALU right register.

The A input to the ALU is right shifted one bit position. The LSB is discarded, and the vacant
MSB is filled with the LSB from the B input to the ALU.

The A input to the ALU is added to the B input, and the CI input is added to the LSB.

The A input to the ALU is added to the B input, and the CO out from the ALU on the previous
cycle is added to the LSB.

The A input to the ALU is added to the inverted B input, and a one is added to the LSB.

The A input to the ALU is added to the inverted B input, and the CI input is added to the
LSB.

The A input to the ALU is added to the inverted B input, and the CO out from the ALU on
the previous cycle is added to the LSB.

The inverted A input to the ALU is added to the B input, and a one is added to the LSB.

The inverted A input to the ALU is added to the B input, and the CI input is added to the
LSB.

The inverted A input to the ALU is added to the B input, and the CO out from the ALU on
the previous cycle is added to the LSB.

Op Code

<00>

<01>

<02>

<03>

<04>

<05>

<06>

<07>

<08>

<09>

<0A>

<0B>

<0C>

<0D>

<0E>

<0F>

Mnemonic

CLRXX

MIAX1

MIACI

MIACO

A2SGN

A2RAL

A2RAR

A2RSX

APBCI

APBCO

AMBX1

AMBCI

AMBCO

BMAX1

BMACI

BMACO

ALU Logical Instructions

Function

The A input to the ALU is logically 'ANDed' with the B input.

The A input to the ALU is logically 'ANDed' with the inverse of the B input.

The inverse of the A input to the ALU is logically 'ANDed' with the B input.

The A input to the ALU is logically 'ORed' with the B input.

The inverse A input to the ALU is logically 'ORed' with the B input.

The A input to the ALU is logically Exclusive-ORed with the B input.

The A input to the ALU is passed to the output.

The inverse of the A input to the ALU is passed to the output.

Op Code

<10>

<11>

<12>

<13>

<14>

<15>

<16>

<17>

Mnemonic

ANXAB

ANANB

ANNAB

ORXAB

ORNAB

XORAB

PASXA

PASNA

PDSP1601 MC

ALU Control Instructions

Function

The BFP flag is programmed to activate when an ALU operation causes an overflow of the
16 bit number range. This flag is logically the exclusive-or of the carry into and out of the
MSB of the ALU. For the most significant Byte this flag indicates that the result of an
arithmetic two's complement operation has overflowed into the sign bit. The output of the
ALU is forced to zero for the duration of this instruction.

The BFP flag is programmed to activate when an ALU operation comes within a factor of
two of causing an overflow of the 16 bit number range. For the most significant Byte this
flag indicates that the result of an arithmetic two's complement operation is within a factor
of two of overflowing into the sign bit. The output of the ALU is forced to zero for the duration
of this instruction.

The BFP flag is programmed to activate when an ALU operation comes within a factor of
four of causing an overflow of the 16 bit number range. For the most significant Byte this
flag indicates that the result of an arithmetic two's complement operation is within a factor
of four of overflowing into the sign bit. The output of the ALU is forced to zero for the duration
of this instruction.

The BFP flag is programmed to activate when an ALU operation causes a result of zero.
The output of the ALU is forced to zero for the duration of this instruction. During the
execution of this instruction the BFP flag will become active.

The ALU will output the binary value 0000000000000001, the MSB on the left.

The ALU will output the binary value 0000000011111111, the MSB on the left.

The ALU will output the binary value 0000000000001111, the MSB on the left.

The ALU will output the binary value 0101010101010101, the MSB on the left.

Op Code

<18>

<19>

<1A>

<1B>

<1C>

<1D>

<1E>

<1F>

Mnemonic

SBFOV

SBFU1

SBFU2

SBFZE

OPONE

OPBYT

OPNIB

OPALT

Barrel Shifter Instructions

Function

The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by
the magnitude of the four bit number present in the SV register. The LSBs are discarded,
and the vacant MSBs are filled with zeros.

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the
magnitude of the four bit number present in the SV register. The MSBs are discarded, and
the vacant LSBs are filled with zeros.

The 16 bit input to the Barrel Shifter is rotated to the right shifted by the number of places
indicated by the magnitude of the four bit number present in the SV register. The LSBs that
exit the 16 bit field to the right, reappear in the vacant MSBs on the left.

The 16 bit input to the Barrel Shifter is rotated to the left shifted by the number of places
indicated by the magnitude of the four bit number present in the SV register. The MSBs
that exit the 16 bit field to the left, reappear in the vacant LSBs on the right.

The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by
the magnitude of the four bit number present in the R1 register. The LSBs are discarded,
and the vacant MSBs are filled with zeros.

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the
magnitude of the four bit number present in the R1 register. The MSBs are discarded, and
the vacant LSBs are filled with zeros.

The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by
the magnitude of the four bit number present in the R2 register. The LSBs are discarded,
and the vacant MSBs are filled with zeros.

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the
magnitude of the four bit number present in the R2 register. The MSBs are discarded, and
the vacant LSBs are filled with zeros.

Op Code

<0>

<1>

<2>

<3>

<4>

<5>

<6>

<7>

Mnemonic

LSRSV

LSLSV

BSRSV

BSLSV

LSRR1

LSLR1

LSRR2

LSLR2

PDSP1601 MC

Function

On the rising edge of CLK at the end of the cycle in which this instruction is executing, the
R1 register will be loaded with the data present on the SV port. The input to the Barrel
Shifter will be passed onto the output unshifted.

On the rising edge of CLK at the end of the cycle in which this instruction is executing, the
R2 register will be loaded with the data present on the SV port. The input to the Barrel
Shifter will be passed onto the output unshifted.

The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by
the magnitude of the four bit number resident within the R1 register. The LSBs are
discarded, and the vacant MSBs are filled with duplicates of the original MSB.
(Sign Extension).

The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by
the magnitude of the four bit number resident within the R2 register. The LSBs are
discarded, and the vacant MSBs are filled with duplicates of the original MSB.
(Sign Extension).

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the
magnitude of the four bit number output from the Priority Encoder. This value is also output
on the SV port (provided

SVOE

is low).

The effect of this operation is to left shift the input by the necessary amount
(max 15 places) to result in the MSB and the next most significant bit being different. This
has the effect of eliminating unnecessary Sign Bits, and hence Normalising the input data.
The MSBs shifted out to the left are discarded, and the vacant LSBs on the right are filled
with zeros.

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the
magnitude of the four bit number output from the Priority Encoder. This value is also loaded
into the R1 register at the end of the cycle, and is output on the SV port (provided

SVOE

is low).
The effect of this operation is to left shift the input by the necessary amount
(max 15 places) to result in the MSB and the next most significant bit being different. This
has the effect of eliminating unnecessary Sign Bits, and hence Normalising the input data.
The MSBs shifted out to the left are discarded, and the vacant LSBs on the right are filled
with zeros.

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the
magnitude of the four bit number output from the Priority Encoder. This value is also loaded
into the R2 register at the end of the cycle, and is output on the SV port (provided

SVOE

Op Code

<8>

<9>

<A>

<B>

<C>

<D>

<E>

<F>

Mnemonic

LR1SV

LR2SV

ASRSV

ASRR1

ASRR2

NRMXX

NRMR1

NRMR2

PDSP1601 MC

Barrel Shifterl or ALU Register Instructions

Function

After the rising edge of CLK at the beginning of the cycle in which this instruction is
executed, the contents of the Right register will appear on the output. On the rising edge
of CLK at the end of the cycle, the data on the register inputs will be loaded into the Left
Register.

After the rising edge of CLK at the beginning of the cycle in which this instruction is
executed, the contents of the Left register will appear on the output. On the rising edge
of CLK at the end of the cycle, the data on the register inputs will be loaded into the Right
Register.

After the rising edge of CLK at the beginning of the cycle in which this instruction is
executed, the contents of the Right register will appear on the output. On the rising edge
of CLK at the end of the cycle no load operation will occur, the register contents will remain
unchanged.

After the rising edge of CLK at the beginning of the cycle in which this instruction is
executed, the contents of the Left register will appear on the output. On the rising edge
of CLK at the end of the cycle no load operation will occur, the register contents will remain
unchanged.

After the rising edge of CLK at the beginning of the cycle in which this instruction is
executed, the input to the register will appear on the output. On the rising edge
of CLK at the end of the cycle no load operation will occur, the register contents will remain
unchanged.

Op Code

<0>

<1>

<2>

<3>

<4>

<5>

<6>

<7>

Mnemonic

LLRRR

LRRLR

LLRLR

LRRRR

LBRLR

NOPRR

NOPLR

NOPPS

PDSP1601 MC

TYPICAL APPLICATION

Select a 16 bit field from each word in a block of 32 bit

words with a 10MHz throughput.

The 16 bit field indicated is to be selected from each 32 bit

word.

(2)

The LS byte is logically right shifted, n-places, the

LSBs being discarded and the MSBs being filled with zeros.
This shifted data is loaded into the shifter register file left
register.

During this cycle the previous contents of this register are

passed through the ALU to the ALU register file left register.

(3)

While the MS byte of the next 32 bit word is shifted in

the Barrel Shifter, the two previous results, resident within the
left registers of the ALU and Shifter Register files are 'ORed'
by the ALU, the result being the desired 16 bit field is loaded
into the ALU register file right register ready to be output on the
next cycle.

The instructions from initialisation are given in Table 6.

MS Byte

LS Byte

MS Bit

16 bits

nbits

The 32 bit words are fed into the B port of the PDSP1601

in two cycles, MS byte first.

The PDSP1601 shift control is initiated by programming

the R1 and R2 registers with n and 16-n respectively.

The shift operation is implemented in three steps:-

(1)

The MS byte is logically left shifted (16-n) places, the

MSBs being discarded and the LSB spaces being filled with
zeros. This shifted data is loaded into the shifter register file
left register.

CLK

1/
2/
3/
4/
5/
6/

CEB

1
1
0
0
0
0

MSA

MARSX
MARSX
MARSX
MARSX
MARSX
MARAX

MARSX

MARAX

MSB

1
1
1
1
1
1

MSS

0
0
0
0
0
0

MSC

0
0
0
0
0
0

CLRXX
PASXA
PASXA
PASXA
PASXA

ORXAB

PASXA

ORXAB

LR1SV
LR2SV

LSLR2

LSRR1

LSLR2

LSRR1

LSLR2

(16-n)

X
X
X

NOPLR
NOPLR
NOPLR
NOPLR

LLRRR
LRRLR

LLRRR

LRRLR

NOPLR
NOPLR
NOPLR

LLRLR
LLRLR
LLRLR

LLRLR

Comment

Clear
Load R1 with n
Load R2 with (16-n)
Shift 1st MS byte
Shift 1st LS byte
OR 1st bytes and
shift 2nd MS byte
Shift 2nd LS byte
and output first result
Shift 3rd LS byte

Repeat instruction pair 5/ and 6/ until all 16 bit fields have been selected.

Table 6

ABSOLUTE MAXIMUM RATINGS

(Note 1)

Supply voltage Vcc

-0.5V to 7.0V

Input voltage V

-0.9V to Vcc + 0.9V

Output voltage V

OUT

-0.9V to Vcc + 0.9V

Clamp diode current per pin I

(see note 2)

�

18mA

Static discharge voltage (HMB)

500V

Storage temperature T

-65

�

C to +150

�

Ambient temperature with
power applied T

amb

Military

-40

�

C to +125

�

Package power dissipation P

TOT

1000mW

NOTES
1. Exceeding these ratings may cause permanent damage.
Functional operation under these conditions is not implied.
2. Maximum dissipation or 1 second should not be exceeded, only
one output to be tested at any one time.

THERMAL CHARACTERISTICS

Package type

�

C/W

PDSP1601 MC

Min.

2.4

2.5

Vdd -1

-10

-50

PDSP1601

Value

Typ.

ELECTRICAL CHARACTERISTICS

Operating Conditions (unless otherwise stated)

AMB

(Military) = -55

�

C to +125

�

C, V

= 5.0V

�

10%, Ground = 0V

Characteristic

* Output high voltage
* Output low voltage
* Input high voltage
* Input low voltage

* Input leakage current
* Vcc current
* Output leakage current
Output S/C current
Input capacitance

Max.

0.4

0.8

0.5

+10

+50

Units

V
V
V
V
V
V

�

Symbol

Static Characteristics

Min.

5
5
5

200
100

40
40

Max.

100
100

0
3
0

100

40
40
40
40

ns
ns
ns
ns
ns
ns
ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
sn

Switching Characteristics

Characteristics

Value

Conditions

= 8mA

= -8mA

CLOCK, OE
CLOCK, OE
GND < V

< V

amb

= -40

�

C to +85

�

GND < V

OUT

< V

= Max

Sub

group

1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3

2 x LSTTL + 20pF
1 x LSTTL + 5pF
1 x LSTTL + 5pF

Input mode
Input mode
20pF load, SV O P mode
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF

9, 10, 11

Units

Sub

group

Conditions

CLK rising edge to C-PORT
CLK rising edge to CO
CLK rising edge to BFP
Setup

CEA

CEB

to CLK rising edge

Hold

CEA

CEB

to CLK rising edge

Setup A or B port inputs to CLK rising edge
Hold A or B port inputs to CLK rising edge
Setup MSA0-1, MSB, MSS, MSC, RA2-0, RS0-2, IA0-4,
IS0-3, to CLK rising edge
Hold RS0-2, IA0-4 to CLK rising edge
Hold IS0-3 to CLK rising edge
Hold MSA0-1, MSB, MSS, MSC, RA0-2 to CLK rising edge
Setup SV to CLK rising edge
Hold SV to CLK rising edge
CLK rising edge to SV

C-PORT Z

Clock period (ALU & Barrel Shifter, serial mode)
Clock period (ALU & Barrel Shifter, parallel mode)
Clock high time
Clock low time

All parameter marked * are tested during production.
Parameters marked are guaranteed by design and characterisation

PDSP1601 MC

Pin No.

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75

Pin No.

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Volt.

N/C
N/C
N/C
N/C

N/C

0V
0V
0V
V1
V1
V1
V1
V1
V1
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V

Volt.

N/C
N/C
N/C
N/C

V1
V1
V1
V1
V1
V1
V1
V1
V1
V1
0V
0V
V1
V1
V1
V1
V1
V1
V1
V1
V1

Volt.

N/C
N/C
N/C
N/C

0V
0V
0V
0V
0V
0V
0V
0V
V1
V1
V1
V1
0V
0V

V1 180K
V1 180K
0V 180K
0V 180K

V1
V1
0V

Pin No.

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

Volt.

N/C
N/C
N/C
N/C
N/C

N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C

N/C

Pin No.

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

Part No:

PDSP1601 MC ALU and Barrel Shifter

Package Type:

GC100

VDD max = +5.0V = V1

N/C = not connected

Fig.4 Life Test/Burn-in connections

NOTE: PDA is 5% and based on groups 1 and 7

TECHNICAL DOCUMENTATION - NOT FOR RESALE

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Tel: +1 (613) 592 2122

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Fax: +44 (0) 1793 518581

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Электронный компонент: PDSP1601MC